1. Field of the Invention
This invention relates to semiconductor memory cells capacitively storing information and more particularly to an improved memory cell having significantly increased capacitance.
2. Description of the Prior Art
Stored charge memory cells of various types are known to the prior art.
U.S. Pat. No. 3,729,719 describes a storage cell using a PNP-NPN combination coupled together, similar to a silicon controlled rectifier circuit but biased such that the combination is prevented from latching so that data may be stored on the inherent capacitance of the collector-base PN junctions of both the NPN and PNP transistors. The data is detected at the emitter of the NPN device.
U.S. Pat. No. 3,423,225 (Joyce-Westinghouse) teaches an integrated circuit which is totally isolated from the substrate by an oxide layer.
U.S. Pat. No. 3,998,673 (Chow-unassigned) teaches an integrated circuit separated by V-grooves or moats which are coated with an oxide and back filled with polysilicon.
IBM Technical Disclosure Bulletin, Vol. 21, #3, August 1978, on page 1004-1006 describes a process for producing a large value base-collector capacitance for semiconductor transistor using etching and oxidation.